This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-392288, filed Dec. 25, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to semiconductor storage devices such as a dynamic memory (DRAM) and a nonvolatile ferroelectric memory.
2. Description of the Related Art
These days, a semiconductor memory is broadly been utilized as a storage device in electronic apparatuses such as, large-sized computers, personal computers, household electric products, and mobile phones. Examples of the semiconductor memory appearing on the market include a volatile dynamic RAM (DRAM), static RAM (SRAM), nonvolatile mask ROM (MROM), FlashE2PROM, and the like. Although particularly the DRAM is a volatile memory, it is superior in terms of low cost and high speed, and occupies a major part of the market at present. On the other hand, a nonvolatile ferroelectric memory using a ferroelectric capacitor has been developed by respective makers, as it has a nonvolatile property, is many rewritable up to 1012 times, and has a read/write time as short as that of a DRAM, and the like.
FIG. 28A shows a circuit diagram of a conventional DRAM, and FIG. 28B shows a signal chart of an operation of the DRAM. As shown in FIG. 28A, one cell transistor CT0 is connected in series with one paraelectric capacitor CC0, one end (capacitor CC0 side) is connected to a plate line (PL), and the other end (cell transistor CT0 side) is connected to a bit line BL. Assuming that an amplitude voltage of the bit line is Vaa, the plate line is usually fixed at xc2xdVaa.
As a problem of the conventional DRAMs, the voltage of a word line WL for selecting a cell needs to be set to a boosted high voltage Vpp, the voltage applied to a memory cell transistor increases as a result, and size reduction of the memory cell transistor (size reduction of a gate oxide film thickness Tox, channel length L, or the like) cannot be realized.
As shown in FIG. 28B, during the operation, the voltage of the word line WL is raised to the voltage Vpp, and data is read into the bit line BL from a cell node CN0 of the DRAM cell. Thereafter, a sense amplifier is operated. When the data is xe2x80x9c1xe2x80x9d data, the voltage of the bit line BL is amplified to Vaa. When the data is xe2x80x9c0xe2x80x9d data, the voltage of the bit line BL is amplified to Vss. The result is rewritten into the cell node CN0. Therefore, when the xe2x80x9c1xe2x80x9d data, that is, Vaa is rewritten into the cell node CN0, a threshold voltage of the cell transistor is set to Vtcell, then Vpp greater than Vaa+Vtcell, and a high voltage, that is, the boosted voltage Vpp is required. In order to lower the voltage Vpp, the voltage Vaa and/or Vtcell may be reduced. However, when the voltage Vaa is lowered, a charge accumulated in the cell decreases, and deterioration of a data holding property and deterioration of a low voltage operation are caused. On the other hand, when Vtcell is lowered, the accumulated charge of the cell leaks to the bit line via the cell transistor, and the data holding property is deteriorated. Therefore, it is difficult to lower the voltage Vpp. For a conventional DRAM, the xe2x80x9c0xe2x80x9d data as well as the xe2x80x9c1xe2x80x9d data are rewritten. With the xe2x80x9c0xe2x80x9d data, the bit line voltage is Vss. The boosted voltage Vpp at maximum is applied between gate and source of the cell transistor, that is, between word line and cell node, as shown by the waveform WL-CN0 on the signal chart.
As described above, in a conventional DRAM, in order to maintain the holding property of the data to be satisfactory, Vtcell cannot be lowered, the high voltage, that is, the boosted voltage Vpp needs to be applied to the cell transistor as a result, and this inhibits a size reduction of the cell transistor. Therefore, a problem occurs that the memory cell size cannot be reduced, and a chip size cannot be reduced. When the size of the cell transistor is forced to be reduced, insulating film collapse, deterioration of an operation property due to a Hot Carrier, and Ioff increase by a short channel effect are generated. Therefore, with a design rule of the same development generation, as compared with a logic LSI, the gate oxide film thickness Tox and channel length L of the cell transistor of the DRAM are large by 30 to 50 percentages in actual circumstances. In addition to the problem that the chip size cannot be small, the problem of slow operation speed occurs in a DRAM-Logic mixed chip in which a logic section is constituted of a transistor having the same size as a cell transistor of the DRAM. To solve the problem, in a conventional technique, for a high-performance DRAM-Logic mixed chip, a transistor having a large Tox and L is used in the DRAM cell transistor, core section requiring the boosted voltage, and I/O section. On the other hand, a transistor having a small Tox and L is used in a DRAM peripheral circuit and the logic section. However, in this case, since two types of transistors are formed, the problem of process cost increase arises.
On the other hand, a method of driving a potential of the plate line PL and lowering Vpp with respect to the conventional DRAM is disclosed in the following:
1) K. Fujishima et al. xe2x80x9cA storage-node-boosted RAM with word line delay compensationxe2x80x9d International Solid-State Circuits Conference Digest Technical Paper, pp. 66-67, 1982;
2) M Aoki et al. xe2x80x9cA 1.5 DRAM for battery-based applicationxe2x80x9d IEEE Journal of Solid-State Circuits, vol. 24, No. 5, pp. 1206-1212, October 1989; and
3) T. Yamauchi et al. xe2x80x9cHigh-performance embedded SOI DRAM architecture for a low-power supplyxe2x80x9d IEEE Journal of Solid-State Circuit, vol. 35, No. 8, pp. 1169-1178, August 2000.
A circuit constitution of the DRAM of this system and a signal chart of the operation are shown in FIGS. 29A, 29B. In the DRAM of this system, the plate line potential PL is amplified between Vss and Vaa, the bit line potential is amplified to Vaa (for xe2x80x9c1xe2x80x9d data) or Vss (for xe2x80x9c0xe2x80x9d data), thereafter the plate line potential PL is lowered to Vss, and xe2x80x9c1xe2x80x9d data of Vpp Vtcell is written into the cell node CN0. Subsequently, the word line potential is lowered to some degree, the xe2x80x9c1xe2x80x9d data is prevented from leaking, the plate line potential PL is lowered to Vaa, and the xe2x80x9c0xe2x80x9d data of Vss is written into the cell node CN0 in this system.
When the plate line potential PL is driven in this manner, as a result, a potential difference Vsig (1:0) of the xe2x80x9c1xe2x80x9d data and xe2x80x9c0xe2x80x9d data is Vsig(1:0)=Vppxe2x88x92Vtcell+Vaa. The data is held to be satisfactory as compared with Vsig(1:0)=Vaa of the DRAM of a conventional plate line potential PL fixed system. According to this system, a doubled signal can be written similarly as use in the ferroelectric memory. However, on the condition of Vpp less than Vaa+Vtcell, Vsig(1:0)=Vppxe2x88x92Vtcell+Vaa less than 2 Vaa. For example, as shown in FIG. 29B, on Vpp=Vaa, Vsig(1:0)=2 Vaaxe2x88x92Vtcell. Consequently, similarly as in the DRAM of FIGS. 28A, 28B, the data is deteriorated because of a drop in the threshold value of the transistor. Moreover, in order to drive the plate line potential PL, the plate line needs to be separated for each memory cell, and the cell size increases. Another problem is that the driving of the plate line takes much time, which delays the operation.
This problem occurs not only in a DRAM but also in a ferroelectric memory. Examples of a conventional ferroelectric memory include a memory whose plate line potential PL is fixed (the paraelectric capacitor of FIG. 28A is replaced with a ferroelectric capacitor), and a memory whose plate line potential PL is driven (the paraelectric capacitor of FIG. 29A is replaced with a ferroelectric capacitor), and the problem is generated similarly as described above. Moreover, for a ferroelectric memory, the inventor of the present application has proposed a new nonvolatile ferroelectric memory in U.S. Pat. No. 5,903,492 characterized by three factors: (1) use of a small memory cell with a 4F2 size; (2) use of an easily manufacturable flat transistor; and (3) use of a general-purpose random access function. In the ferroelectric memory disclosed in the U.S. Pat. No. 5,903,492, one memory cell is constituted by connecting the cell transistor in parallel to the ferroelectric capacitor, one memory cell block is constituted by connecting a plurality of memory cells in series, one end of the block is connected to the bit line via a block selection transistor, and the other end of the block is connected to the plate. Also in the ferroelectric memory disclosed in the U.S. Pat. No. 5,903,492, the systems in which the plate line potential PL is fixed, and the system whose plate line potential PL is driven, are present, resulting in the aforementioned problem.
As described above, in a conventional DRAM, conventional ferroelectric memory, or the ferroelectric memory disclosed in the U.S. Pat. No. 5,903,492, in order to suppress an OFF current of the cell transistor, and maintain a data holding time, the voltage applied to the memory cell transistor increases. As a result, there is a problem that it is difficult to reduce the cell transistor and the cell size cannot be reduced in order to secure reliability. Moreover, in a transistor constitution which has one gate oxide film thickness, the transistor of the peripheral circuit or the mixed logic section cannot be reduced, resulting in a deterioration in operation performance. Moreover, with use of a transistor which has two gate oxide film thicknesses, the performance of the peripheral circuit or the mixed logic section is raised, but process cost disadvantageously increases.
According to a first aspect of the present invention, there is provided a semiconductor memory device comprising a semiconductor memory circuit which includes a memory cell array including a plurality of memory cells arranged in a matrix form each constituted of a cell transistor and a capacitor whose one end is connected to a plate line, a plurality of word lines, and a plurality of bit lines constituting a pair of bit lines connected to a sense amplifier; and a control circuit which controls the semiconductor memory circuit to set the bit lines to a high level to write xe2x80x9c1xe2x80x9d data into the memory cells regardless of a logic level of data to be written, in a state where a potential of a gate of the cell transistor of each memory cell is raised from a first potential of a standby time to a second potential of an active time, and thereafter to set the bit lines to a low level to write xe2x80x9c0xe2x80x9d data into the memory cells with xe2x80x9c0xe2x80x9d data to be written, in a state where the potential of the gate of the cell transistor is changed to a third potential higher than the first potential and lower than the second potential.
According to a second aspect of the present invention, there is provided a semiconductor memory device comprising a semiconductor memory circuit which includes a memory cell array including a plurality of memory cells arranged in a matrix form each constituted of a cell transistor and a paraelectric capacitor having one end connected to a source of the cell transistor, a plurality of word lines connected to gates of the cell transistors of the memory cells, a plurality of pairs of bit lines connected to drains of the cell transistors of the memory cells, a plate line connected to the other end of the paraelectric capacitor, and a plurality of sense amplifier circuits each connected to a corresponding pair of bit lines; and a control circuit which controls the semiconductor memory circuit in an operation time to raise the word lines to be selected from a first potential to a second potential to read cell data from the memory cells onto the bit lines, thereafter set the bit lines to a high level to write xe2x80x9c1xe2x80x9d data into the memory cells regardless of a logic level of data to be written, thereafter set the selected word lines to a third potential lower than the second potential and higher than the first potential, set the bit lines to a low level with xe2x80x9c0xe2x80x9d data to be written to write xe2x80x9c0xe2x80x9d data into the memory cells, and thereafter to lower the selected word lines to the first potential.
According to a third aspect of the present invention, there is provided a semiconductor memory device comprising a semiconductor memory circuit which includes a memory cell array including a plurality of memory cells arranged in a matrix form each constituted of a cell transistor and a ferroelectric capacitor having one end connected to a source of the cell transistor, a plurality of word lines connected to gates of the cell transistors of the memory cells, a plurality of pairs of bit lines connected to drains of the cell transistors of the memory cells, a plate line connected to the other end of the ferrolelectric capacitor, and a plurality of sense amplifier circuits each connected to a corresponding pair of bit lines; and a control circuit which controls the semiconductor memory circuit in an operation time to raise the word lines to be selected from a first potential to a second potential to read cell data from the memory cells onto the bit lines, thereafter set the bit lines to a high level to write xe2x80x9c1xe2x80x9d data into the memory cells regardless of a logic level of data to be written, thereafter set the selected word lines to a third potential lower than the second potential and higher than the first potential, set the bit lines to a low level with xe2x80x9c0xe2x80x9d data to be written to write xe2x80x9c0xe2x80x9d data into the memory cells, and thereafter to lower the selected word lines to the first potential.
According to a fourth aspect of the present invention, there is provided a semiconductor memory device comprising a semiconductor memory circuit which includes a memory cell array including a plurality of memory cells arranged in a matrix form each constituted of a cell transistor and a ferroelectric capacitor having one end connected to a source of the cell transistor, a plurality of word lines connected to gates of the cell transistors of the memory cells, a plurality of pairs of bit lines connected to drains of the cell transistors of the memory cells, a plate line connected to the other end of the ferrolelectric capacitor, and a plurality of sense amplifier circuits each connected to a corresponding pair of bit lines; and a control circuit which controls the semiconductor memory circuit in an operation time to raise the word lines to be selected from a first potential to a third potential and raise the plate line from the first potential to the third potential and subsequently lower the plate line to the first potential, amplify a signal by the sense amplifiers in this state, thereafter set the bit lines to a high level and raise the word line to a second potential higher than the third potential to write xe2x80x9c1xe2x80x9d into the memory cells regardless of a logic level of data to be written, thereafter lower the word line to the third potential, again raise the plate line to the third potential, thereafter set the bit line to a low level with xe2x80x9c0xe2x80x9d data to be written to write xe2x80x9c0xe2x80x9d data into the memory cells, and thereafter to lower the selected word lines to the first potential.
According to a fifth aspect of the present invention, there is provided a semiconductor memory device comprising a semiconductor memory circuit which includes a memory cell array including a plurality of memory cells in a matrix form each constituted of a cell transistor and a ferroelectric capacitor connected in parallel between source and drain terminals of the cell transistor, a plurality of word lines connected to gates of the cell transistors, a plurality of pairs of bit lines, a plurality of block selection transistors each connected between one end of the memory cells connected in series in a corresponding row and a corresponding bit line, a plurality of plate lines each connected to the other end of the memory cells connected in series in the corresponding row, and a plurality of sense amplifier circuits each connected to a corresponding pair of bit lines; and a control circuit which controls the semiconductor memory circuit in an operation time to raise gate potentials of the block selection transistors to be selected from a first potential to a second potential to read cell data from the memory cells of the selected block selection transistors onto the bit lines, thereafter set the bit lines to a high level to write xe2x80x9c1xe2x80x9d data into the memory cells regardless of a logic level of data to be written, thereafter set the gate potentials of the selected block selection transistors to a third potential lower than the second potential and higher than the first potential, set the bit line to a low level with xe2x80x9c1xe2x80x9d data to be written to write xe2x80x9c0xe2x80x9d data into the memory cells, and thereafter to lower the gate potentials of the selected block selection transistors to the first potential.